Since its debut in 2004, the current generation of high-level synthesis (HLS) tools has made tremendous progress in terms of both quality of results (QoR) and wider applicability. The success of this ...

In order to perform architectural exploration, performance analysis and optimization, early validation of software, improved productivity in hardware development and many other tasks, the industry ...

High-level design (HLD) represents a hardware design at a more abstract level than register transfer level (RTL). A high-level synthesis (HLS) tool then can be used to produce the RTL necessary to ...

System-Level Design moderated a discussion about the future of SystemC with Thomas Alsop, corporate design solution expert at Intel; Ambar Sarkar, chief verification technologist at Paradigm Works; ...

SAN JOSE, Calif. — In a push to establish a new design verification standard, the Open SystemC Initiative last week announced the SystemC Verification standard, based on Cadence Design Systems Inc.'s ...

SAN JOSE, CA--(Marketwired - Feb 24, 2015) - OneSpin® Solutions, provider of innovative formal verification and formal equivalence checking solutions, today announced that OneSpin 360 DV™ now supports ...

For some time now, advocates of various high-level design languages have sparred over which approach to design at a level of abstraction above register transfer level ...

In this paper, we present an extension of the SystemC simulator in order to allow its execution on an IA-64 platform. Our approach relies on adding to SystemC a new user thread package in a simple way ...

WALTHAM, Mass.--May 30, 2006--Bluespec Inc., developer of the only ESL synthesis toolset for control logic and complex datapaths in chip design, today announced ESL Synthesis support for SystemC, the ...

STATE takes a SystemC design as input and transforms it into a corresponding UPPAAL timed automata model. The transformation is based on a formal semantics defined for SystemC in ...