Do you have a plan? Project management is all about planning and execution. If everyone properly plans their verification project, why do quality problems and schedule slips persist? It really comes ...

As verification engineers move to more-sophisticated techniques for system-on-chip (SoC) designs, their planning process is evolving as well. Traditional test-based planning is being supplanted by ...

From my product development experiences, entering into Design Verification and Design Validation is always bittersweet. Exciting because yes, to get to Design Verification means that we have ...

The purpose of the verification plan, or vplan as we call it, is to capture all the verification goals needed to prove that the device works as specified. It’s a big responsibility! Getting it right ...

Verification of complex SoCs (System on Chip) require tracking of all low level data (i.e. Regression results, Functional and Code coverage). Usually, verification engineers do this type of tracking ...

Formal verification-tool start-up Jasper Design Automation is offering a free tool to help IC-verification teams generate and track verification plans. Craig Cochran, vice president of marketing at ...

Verification plans are rapidly evolving from mechanisms to track verification progress into multi-faceted coordination vehicles for several teams with disparate goals, using complex resource ...